1. Field of the Invention
The present invention relates in general to a programmable phase shifter for phase shifting a periodic input signal by an adjustable amount, and in particular to a programmable phase shifter that can be easily calibrated to provide a phase shift that is a linear function of the value of input control data.
2. Description of Related Art
FIG. 1 illustrates a prior art programmable phase shifter 10 for phase shifting a periodic input signal T.sub.0 by an adjustable phase angle to produce an output signal T.sub.OUT. The phase angle is controlled by 10-bit input control data N. Ideally phase shifter 10 should provide a phase shift between T.sub.0 and T.sub.OUT that is a linear function of the value of input control data N. However, as explained below, phase shifter 10 has inherent sources of error that cause the phase shift to deviate from the desired linear function of the value of N.
Phase shifter 10 includes a tapped delay line 12 formed by a set of delay elements 14 connected in series for successively delaying the T.sub.0 signal to produce a set of 32 "tap" signals TAP.sub.1 -TAP.sub.32 at the element outputs. A delay element 14 may be, for example, a logic gate. Each successive tap signal TAP.sub.1 -TAP.sub.32 is inverted and delayed from its preceding tap signal by the inherent delay of a delay element 14. The T.sub.0 and TAP.sub.32 signals provide inputs to a conventional delay lock loop (DLL) controller 16 providing a BIAS signal to each delay element 14. The BIAS signal controls the switching speed of the delay elements and therefore controls the delay of each delay element 14. DLL controller 16 adjusts the BIAS signal so that the TAP.sub.32 signal is phase locked to the T.sub.o signal. Thus the total delay between T.sub.0 and TAP.sub.32 is equal to the period P.sub.0 of T.sub.0. When all delay elements 14 are similar, each element's delay is close to the average element delay of P.sub.0 /32.
The tap signals TAP.sub.1 -TAP.sub.32 are inputs to a multiplexer 18 controlled by the upper five bits NH of 10-bit input control data N. Multiplexer 18 selects one of its input signals TAP.sub.1 -TAP.sub.32 and provides it as an input signal T.sub.S to a programmable delay circuit 20. Delay circuit 20 delays the T.sub.S signal by from 0 to 31 "unit delays" where a unit delay is P.sub.0 /(32*N.sub.MAX). The amount of the delay provided by delay circuit 20 is selected by the lower 5 bits NL of control data N. Thus the 10-bit input control data N controls the phase shift between T.sub.0 and T.sub.OUT with a resolution of P.sub.0 /2.sup.10.
FIG. 2 illustrates a typical prior art programmable delay circuit 20 in more detailed block diagram form. Delay circuit 20 includes a set of 2.sup.5 delay elements 22, each delay element 22 delaying the T.sub.S signal to provide a separate input to a multiplexer 26 controlled by the five NL bits. The delay provided by each delay element 24 is controlled by the size of a capacitor 24 within the delay element.
While the resolution of phase shifter 10 of FIG. 1 is nominally P.sub.0 /2.sup.10, differences in the delays provided by delay elements 14 affect the accuracy of the phase shift it provides. One major source of error is power supply noise. In synchronous circuits using T.sub.0 as the primarily reference clock for synchronous operations, the largest component of power supply noise typically comes from the T.sub.0 signal. The power supply noise is therefore coherent with the T.sub.0 signal. The delay of each delay element 14 changes with its power supply voltage. Thus the delay of each delay element 14 varies over time, but does so periodically in a manner that is synchronized to the movement of T.sub.0 pulses through delay line 12. When a T.sub.0 pulse is passing through any particular delay element 14, the power supply voltage provided to that delay element 14 is the same as it is when any other T.sub.0 pulse passes through that same delay element 14. Thus despite the presence of power supply noise, any particular delay element 14 delays each successive T.sub.0 pulse by the same amount. However since each delay element 14 carries out its delay operation at a different time relative to a T.sub.0 clock cycle, and since the power supply varies during each T.sub.0 clock cycle, each delay element 14 receives a different power supply voltage at the time it is actually delaying the T.sub.0 pulse. Thus the coherent noise in the power supply makes each delay element 14 provide a different delay. Due to the variation in delays of delay elements 14, the phase shift between T.sub.0 and T.sub.OUT provided by phase shifter 10 is a non-linear function of its the input control data N.
What is needed is a phase shifter employing a tapped delay line in which the phase shift it provides is a linear function of input data N despite variation in delay provided by the delay line stages.